1. Field of the Invention
The invention relates to an electrostatic discharge (ESD) protection circuit, and more particularly to an ESD protection circuit with high power supply rejection ratio (PSRR).
2. Description of the Related Art
An electrostatic discharge (ESD) event is an important reliability issue for integrated circuits (ICs). To meet component-level ESD reliability, on-chip ESD protection circuits are implemented in the input/output (I/O) cells and power/ground cells of complementary metal-oxide semiconductor (CMOS) ICs.
With the continued miniaturization of IC devices, the current trend in the sub-micron CMOS technology is to produce integrated circuits with shallower junction depths, thinner gate oxides, lightly-doped drain (LDD) structures, shallow trench isolation structures, and silicide processes. However, the advanced IC devices also become more susceptible to ESD damage. ESD phenomenon occurs when excess charges are transmitted from the I/O pin to the integrated circuit too quickly, which damages the internal circuit. Therefore, ESD protection circuits are built onto the chip to protect the devices and circuits of the IC against ESD damage.